The present invention relates to flash memory 10 devices and, more particularly, to a program method which can prevent a disturb phenomenon without increasing a program speed.
Recently, there has been an increasing demand for semiconductor memory devices that can be electrically programmed and erased and retain data without the data being lost even when power is cut off. Further, in order to develop large-capacity memory devices capable of storing lots of data, a high-integration technique of a memory cell memory cell has been developed. To this end, a NAND type flash memory device in which a plurality of memory cells are connected in series to form one string and a plurality of the strings form one memory cell array has been proposed.
In general, a flash memory cell includes a gate in which a tunnel insulating layer, a floating gate, a dielectric layer and a control gate are stacked on a semiconductor substrate, and a junction region formed by the semiconductor substrate at both sides of the gate. The flash memory cell is programmed as hot electrons are injected into the floating gate, and is erased as the injected electrons are discharged by F-N tunneling.
In more detail, in the case of NOR type flash, the program operation of the flash memory cell is performed in a state where a source region of a memory cell and the semiconductor substrate, that is, a bulk region are grounded, the control gate is applied with a positive high voltage (that is, a program voltage, Vpp) (for example, 15V to 20V), and voltage (for example, 5 to 6V) for program is applied to the drain of the memory cell. In the case of NAND type flash, the program operation of the flash memory cell is performed in a state where a positive voltage is applied to a drain select line of a cell array of a string structure to which a plurality of memory cells are connected, voltage of 0V is applied to a source select line of the cell array of the string structure, and 0V is applied to a bit line and the substrate, and a program voltage of 15V to 20V is applied to a word line.
FIG. 1 is a circuit diagram of a cell array of a general flash memory device.
First to sixteenth cells c1 to c16, a string select transistor d and a source select transistor s are connected in series to a first string st1. The first cell c1 has a drain connected to a first bit line b1 through the string select transistor d, and the sixteenth cell c16 has a source connected to a common source line s1 through the source select transistor s. A second string st2 has the same structure as that of the first string st1. The gates of cells existing in the same longitudinal direction (a vertical direction to the bit line) line are connected to corresponding word lines. Though not illustrated in the drawing, the plurality of strings form flash memory.
For a program operation, a selected bit line is applied with ground voltage 0V, and the unselected bit lines are applied with power supply voltage Vcc. Furthermore, a selected word line is applied with program voltage Vpgm (for example 18V), a drain select line DSL1 is applied with power supply voltage (for example 4.5V), and a source select line SSL1 is applied with ground voltage 0V. The unselected word lines are also applied with a pass voltage Vpass (for example 10V). Selected cells under these voltage conditions are programmed individually.
In the program method of the flash memory device, threshold voltage distributions of the program cell are important. A program cell having a threshold voltage that is too high can be turned off at a specific read voltage Vread. Thus, there may be a case where a bypass function cannot be performed. Above phenomenon occurs due to a cell with a very high program speed in the same program voltage. Therefore, in order to prevent the phenomenon, threshold voltage distributions of memory cells are uniformly controlled by means of an Incremental Step Pulse Program (ISPP) method in which the program operation is performed at a relatively low program voltage in the case of a cell having a fast program speed and at a relatively high program voltage in the case of a cell having a slow program speed.
However, the program speed of cells in the memory device may vary depending on the process variation, such as, the thickness of the tunnel insulating layer, which affects the program speed. Accordingly, a start bias in the ISPP method begins at a very low voltage in order to include all these process variations. In other words, if an overall program speed is fast due to process variation, the start bias begins low from the beginning. In the case of a cell having a slower program speed, the program voltage must be increased.
FIG. 2 illustrates a program operation performed using an incremental step-pulse programming (ISPP) operation. The X-axis denotes the number of program cycles performed, and the Y-axis denotes the percentage of the cells that have been programmed properly. All of the memory cells are programmed after eight program cycles.
In the ISPP method, as in FIG. 2, an overall program operation time is increased. For example, if a start bias begins at a low voltage 1.5V, a program cycle number corresponding to 1.5V is increased. If Vstep is 0.3V and a program cycle is 50 μs, the program operation time is increased by as much as about 250 μs. A program disturb phenomenon, in which a cell-inhibited cell undergoes a shallow program and an erase cell loses its characteristics, is also generated. The ending bias of the program operation is set for the purpose of a cell having a slow program speed. Accordingly, there may occur a problem in which a cell having a fast program speed loses erase cell's characteristics even at the same ending voltage.